IC chips typically include active or passive electrical components (e.g., transistors, diodes) connected together by metal lines formed in successive layers above the surface of the semiconductor material. The metal lines are separated by layers of an insulating material commonly referred to as interlayer dielectric.
As is well known, the size of IC chips has shrunk dramatically, enabling a higher packing density of electrical components to be placed in a given area of the chip and increasing the speed at which the circuitry included in the chip can operate. These increases in operating speed are partially offset, however, by the increased resistance-capacitance (RC) delays that result from the closer spacing between adjacent metal lines.
Since capacitance is directly proportional to the dielectric constant (k), the RC delays in ICs, can be reduced through the use of a low-dielectric-constant material as the insulating material. The need for lower dielectric constant materials for use as interlayer dielectrics for modem semiconductor technology is well known in the semiconductor industry. For example, silicon dioxide (SiO2), has long been used as a dielectric for integrated circuits because of its excellent thermal stability and relatively good dielectric properties (k˜4.2). However, the need exists for a dielectric material which is suitable for use in ICs which has a lower dielectric constant than SiO2. After extensive study, a very promising dielectric material has been identified, known as fluorosilicate glass (FSG), which has a dielectric constant (k) of less than 3.7.
The dielectric constant of an FSG layer can be reduced by increasing the doping concentration of fluorine within the FSG layer. A problem with this, however, is that with increased fluorine concentrations hydrofluoric acid (HF) is more likely to form if the FSG layer is exposed to moisture. The generation of HF decreases the stability and adhesion properties of the FSG film. In addition, fluorine can attack Al and Cu wiring to cause resistance changes and reliability problems.
One solution to this problem has been to form a relatively thick silicon rich oxide (SRO) cap on the FSG layer in an attempt to shield the layer from moisture and other foreign materials. Since SRO has a high k, this increases the overall dielectric constant of the structure significantly. In addition, in the damascene process that is used with Cu layers the SRO cap is typically removed by chemical-mechanical planarization (CMP), thereby exposing the fluorine rich FSG layer to moisture and causing the formation of HF.
Accordingly, there is a real need for an FSG layer that has a low dielectric constant and yet is stable enough to be used with a damascene process.